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S3C2440
PDA, Smartphone, Telematics
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SAMSUNG's S3C24440X is designed to provide hand-held devices and general applications with low-power, and high-performance micro-controller solution in small die size.
 
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General Description
This manual describes SAMSUNG's S3C2440X 16/32-bit RISC microprocessor.
SAMSUNG's S3C24440X is designed to provide hand-held devices and general applications with low-power, and high-performance micro-controller solution in small die size. To reduce total system cost, the S3C2440X includes the following components separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD Controller (STN & TFT), NAND Flash Boot Loader, System Manager (chip select logic and SDRAM Controller), 3-ch UART, 4-ch DMA, 4-ch Timers with PWM, I/O Ports, RTC, 8-ch 10-bit AD C and Touch Screen Interface, Camera interface, IIC-BUS Interface, IIS-BUS Interface, USB Host, USB Device, SD Host & Multi-Media Card Interface, 2-ch SPI and PLL for clock generation.
The S3C2440X has been developed using an ARM920T core, 0.13um CMOS standard cells and a memory complier. Its low-power, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive applications. It adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA).
The S3C2440X offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length.
By providing a complete set of common system peripherals, the S3C2440X minimizes overall system costs and eliminates the need to configure additional components. The integrated on-chip functions that are described in this document include:

1.2V internal, 1.8V/2.5V/3.3V memory, 3.3V external I/O microprocessor with 16KB I-Cache/16KB D-Cache/MMU
External memory controller (SDRAM Control and Chip Select logic)
LCD controller (up to 4K color STN and 256K color TFT) with 1-ch LCD-dedicated DMA
4-ch DMAs with external request pins
3-ch UART (IrDA1.0, 64-Byte Tx FIFO, and 64-Byte Rx FIFO) / 2-ch SPI
1-ch multi-master IIC-BUS/1-ch IIS-BUS controller
SD Host interface version 1.0 & Multi-Media Card Protocol version 2.11 compatible
2-port USB Host /1- port USB Device (ver 1.1)
4-ch PWM timers & 1-ch internal timer
Watch Dog Timer
130-bit general purpose I/O ports / 24-ch external interrupt source
Power control: Normal, Slow, Idle and Sleep mode
8-ch 10-bit ADC and Touch screen interface
RTC with calendar function
On-chip clock generator with PLL
 DOCUMENTS
File Rev # Size Updated Date
User's Manual
0.06 7.04 MB 2003-10-16
Application Note
0.17 10.16 MB 2003-09-30
e-brochure
  1.36 MB 2004-01-26
 TOOLS
UTILITY
File Rev # Size Updated Date
ADW initialization script file
(Type "ob armsd.ini" in the ADW command window)
  141 B 2004-11-03
DNW
(USB/Serial download utility for WINDOWS 98/Me/NT/2000)
0.50A 4.01 MB 2004-01-26
GNU make utility
3.78 62.42 KB 2004-01-26
ARM SDT 2.50 patch file
(SDT 2.5x should use the embedded library in the C:ARM25xLIBEMBEDDED. If not, the C library may not work.)
2.5 182.28 KB 2004-01-26
FRATE
(LCD frame rate calculation utility)
0.11 52.20 KB 2004-01-26
EVALUATION  BOARD
File Rev # Size Updated Date
SEC JTAG Flash(SJF) Program
0.1 624.58 KB 2003-10-01
S3C2440X BSDL file
  41.13 KB 2003-10-01
SMDK2440X Buffer Control Chip Source Code
  84.02 KB 2004-01-05
Schematic Diagram
0.17 1.14 MB 2003-10-01