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S3C24A0
System-On-Chip Solution for High-End, Multimedia Handsets
제품 기본 설명
The S3C24A0A is a 16/32-bit RISC microprocessor, designed to provide a cost-effective, low power, and high performance micro-controller solution for mobile phones and general applications. To provide a sufficient H/W performance for the 2.5G & 3G communication services, the S3C24A0A adopts dual-32-bit bus architecture and includes many powerful hardware accelerators for the motion video processing, serial communications, and etc. For the real time video conferencing, an optimized MPEG4 H/W Encoder/Decoder is integrated.
 
상세설명
To reduce total system cost and enhance overall functionality, the S3C24A0A also includes following components: separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD controller (TFT), Camera Interface, MPEG-4 ME, MC, DCTQ, NAND Flash Boot loader, System Manager (power management & etc.), SDRAM controller, 2-ch UART, 4-ch DMA, 4-ch Timers, General I/O Ports, IICBUS interface, USB Host, SD Host & Multi-Media Card Interface, Memory Stick Interface, PLL for clock generation & etc. The S3C24A0A can be used as a most powerful Application Processor for mobiles phones. For this application, the S3C24A0A has a Modem Interface to communicate with various Modem Chips.

The S3C24A0A is developed using an ARM926EJ-S core, advanced 0.13um CMOS standard cells and memory compliers. Its low-power, simple, elegant and fully static-design scheme is particularly suitable for cost-sensitive and power-sensitive applications. Also, the S3C24A0A adopts a de-facto standard bus architecture – the AMBA (Advanced Microcontroller Bus Architecture).

One of the outstanding features of the S3C24A0A is it’s CPU core, a 16/32-bit ARM926EJ-S RISC processor designed by ARM, Ltd. The ARM926EJ-S is a single chip MCU and Java enabled microprocessor. The ARM926EJ-S also implements the MMU, the AMBA BUS, and the Harvard cache architecture with separate 16KB instruction and 16KB data caches, each cache with an 8-word line length.

By providing a complete set of common system peripherals, the S3C24A0A minimizes overall system costs and eliminates the need to configure additional components.
Features
This section will explain the features of the S3C24A0A. Figure 1-1 is an overall block diagram of the S3C24A0A.
 
 
Microprocessor and Overall Architecture
 
SoC (System-on-Chip) for mobile phones and general embedded applications.
16/32-Bit RISC architecture and powerful instruction set with ARM926EJ-S CPU core.
ARM’s Jazelle Java technology enhanced ARM architecture MMU to support WinCE, Symbian and Linux
Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main memory
bandwidth and latency on performance
4 way set-associative cache with I-Cache (16KB) and D-Cache (16KB).
8-words per line with one valid bit and two dirty bits per line
Pseudo random or round robin replacement algorithm.
Write through or write back cache operation to update the main memory.
The write buffer can hold 16 words of data and four addresses.
ARM926EJ-S core supports the ARM debug architecture
Internal AMBA (Advanced Microcontroller Bus Architecture) (AMBA2.0, AHB/APB)
Dual AHB bus for high-performance processing (AHB-I & AHB-S)
 
 
Memory Subsystem
 
High bandwidth Memory subsystem with two access channels (accesses from two AHB buses) and three channel
memory ports
Double the bandwidth with the simultaneous access capability
ROM/SRAM/NOR-Flash/NAND-Flash channel
One SDRAM channels
Up to 1GB Address space
Low-power SDRAM interface support : Mobile SDRAM function
- DS: Driver Strength Control
- TCSR: Temperature Compensated Self-Refresh Control
- PASR: Partial Array Self-Refresh Control
NAND Flash Boot Loader with the ECC circuitry to support booting from NAND Flash
- 4KB Stepping Stone
- Support 1G, 2G bit NAND Flash
 
 
General Peripherals
 
Interrupt Controller
- 61 Interrupt sources
(1 Watch Dog Timer, 5 Timer, 6 UART, 18 External Interrupts, 4 DMA, 2 RTC, 3 ADC, 1 I2C, 1 AC97, 1NAND Flash, 1 IrDA,
1 Memory Stick, 2 SPI, 1 SDI, 2 USB (Host and Device), 1 Keypad, 1 Modem Interface, 2 Camera Interface, 4 MPEG, 2 LCD,
1 Battery Fault, 1 Post)
- Level/Edge mode on external interrupt source.
- Programmable polarity of edge and level.
- Supports FIQ (Fast Interrupt request) for very urgent interrupt request.
Timer with PWM (Pulse Width Modulation)
- 4-ch 16-bit Timer with PWM / 1-ch 16-bit internal timer with DMA-based or interrupt-based operation
- Programmable duty cycle, frequency, and polarity
- Dead-zone generation.
- Support external clock source.
16-bit Watchdog Timer.
- Interrupt request or system reset at time-out.
4-ch DMA controller.
- Support memory to memory, IO to memory, memory to IO, and IO to IO
- Burst transfer mode to enhance the transfer rate.
RTC (Real Time Clock)
- Full clock feature: msec, sec, min, hour, day, date, week, month, year.
- 32.768 KHz operation
- Alarm interrupt
- Time-tick interrupt
 
 
Serial Communication
 
UART
- 2-channel UART with DMA-based or interrupt-based operation
- Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive
- Supports external clock for the UART operation (XuCLK)
- Programmable baud rate
- Supports IrDA 1.0
- Loop back mode for testing
- Each channel has internal 64-byte Tx FIFO and 64-byte Rx FIFO
IrDA
- Support IrDA 1.1 (1.152Mbps and 4Mbps)
- Support FIFO operation in the MIR and FIR mode
- Configurable FIFO Size (16-byte or 64-byte)
- Support Back-to-Back Transactions
- Support Software Selection Temic-IBM or HP Transceiver
- Support Little-endian access
IIC-Bus Interface
- 1-ch Multi-Master IIC-Bus
- Serial, 8-bit oriented and bi-directional data transfers can be made at up to 100 Kbit/s in the standard mode
IIS-Bus Interface
- 1-ch IIS-bus for the audio-codec interface with DMA-based operation
- Serial, 8/16-bit per channel data transfers
- 128 Bytes (64-Byte + 64-Byte) FIFO for receive/transmit
- Supports IIS format and MSB-justified data format
SPI Interface
- 2-ch Serial Peripheral Interface Protocol version 2.11 compatible
- 2x8 bits Shift register for receive/transmit.
- DMA-based or interrupt-based operation.
AC97 Audio-CODEC Interface
- 48kHz 16-bit sampling
- 1-ch stereo PCM inputs / 1-ch stereo PCM outputs / 1-ch MIC input
USB Host
- 2-port USB Host
- Complies with OHCI Rev. 1.0
- Compatible with the USB Specification version 1.1
USB Device
- 1-port USB Device
- 5 End-points for USB Device
- Compatible with the USB Specification version 1.1
 
 
Parallel Communication
 
Modem Chip Interface
- 8-bit Asynchronous SRAM interface-style interface
- On-chip 2KB dual-ported SRAM buffer
- Interrupt Request for Data Exchange
- Programmable Interrupt Port Address
32-bit GPIO
- Fully configurable 32-bit GPIO
 
 
Image and Video Processing
 
Camera Inteface
- ITU601/ITU656 YCbCr 4:2:2 8/16-bit mode
- Image down scaling capability for variable applications
- Digital Zoom-In
- Image X, Y-flip, 180 rotation
- Input Image Window Cut
- Two master for dedicated DMA operation
- Programmable burst length for DMA operation
- Programmable polarity of video sync signals
- Wide horizontal line buffer (maximum 2048 pixel)
- Up to 4M pixel resolution support for scaled image (image preview or motion video capturing) and 16M pixel for unscaled
image (JPEG)
- Format conversion from YCrCb 4:2:2 to 4:2:0 for codec, and to RGB 4:4:4 for preview
Hardware Accelerated MPEG4 Video Encoding/Decoding
- A AHB Interface
- Realtime MPEG-4 Video Encoding & Decoding
- Up to Simple Profile at Level 3 (352x288 at 30fps)
- Supports H.263 Base Line
MPEG-4 ME (Motion Estimation)
- Highly optimized hard-wired engine
- Unrestricted Mode and Advanced Prediction Mode (4MV)
- Use the advanced MRMCS algorithm
- Half-pel search
- Programmable Image size up to 2048x2048
- Padding for Macro-block basis
- Search Range: [-16, 15.5]
- Intra/Inter Mode Decision MC (Motion Compensation)
MC (Motion Compensation)
- Highly optimized hard-wired engine
- Unrestricted Mode and Advanced Prediction Mode (4MV)
- Half-pel search
- Programmable Image size up to 2048x2048
- Dedicated DMA
- Macroblock-based Pading
- Search Range: [-64, 63.5]
DCTQ
- DCT/IDCT/Q/IQ operations
- AMBA AHB Interface
- Support MPEG-4 Simple Profile Level 3 / H.263 Base-Line
- Support programmable image size up to 4096x4096
- Macroblock-based processing
- Rate Control by Qp Information
- Local DMA
- Support MPEG-4 Encoding / Decoding
- Support JPEG DCT / IDCT Operation
- Operation unit : 1MB(MacroBlock) ~ 1 Frame
VLX
- VLC/VLD operations
- AMBA AHB Interface
- Support MPEG4 Simple Profile Level 3/ H.263. Baseline
- Macro block-based processing
- Dedicated DMA
- Only DCTQ coefficient VLC/VLD operation
- Only DC prediction operation in VLC
Post Processor
- Dedicate DMA with Offset Address
- 3 Channel Scaling Pipelines for Video/Graphis Signal
- Input Format: YCbCr4:2:0, YCbCr4:2:2, or RGB 16b/24b
- Output Format: RGB 16b/24b
- Programmable Image Size (Source up to 4096x4096, Destination up to 2048x2048)
- Programmable Scale Ratio (Up-scale: up to Max. Destination Size, Down-scale: ~>1/64 in X & Y)
- Format Conversion for Video Signal (YCbCr4:2:0 or YCbCr4:2:2)
- Color Space Conversion (YCbCr2RGB)
- Separate Processing Clock from AHB Interface Clock
 
 
Display Control
 
TFT LCD Interface
- 18-bit Parallel or 6bit*3 Interface
- 1/2/4/8-bpp Palletized or 8/16/18-bpp Non-Palletized Color-TFF support
- Supports 640x480, 320x240, 176x192 and others
- Up to 16 Mbyte virtual screen size
- Supports Multiple Virtual Display Screen (Supports Hardware Horizontal/Vertical Scrolling)
- Programmable timing control for different display panels
- Dual Buffer
OSD (On Screen Display)
- Realtime overlay plane multiplexing
- Programmable OSD window positioning
- Per-pixel alpha blending for 18-bpp OSD images
- Fixed alpha-value for 8-/16-/18-bpp OSD image
- 56-level alpha blending
- 24-bit color key support
- Dual buffer
 
 
Input Devices
 
Keypad Interface
- Provides internal debouncing filter
- 5-input, 5-output pins for key scan in/out
A/D Converter and Touch Screen Interface
- 8-ch multiplexed ADC
- Max. 500K samples/sec and 10-bit resolution
 
 
Storage Devices
 
SD Host
- Compatible with SD Memory Card Protocol version 1.0
- Compatible with SDIO Card Protocol version 1.0
- 64 Bytes FIFO for Tx/Rx
- DMA based or Interrupt based operation
- Compatible with Multimedia Card Protocol version 2.11
Memory Stick Host
- Memory Stick version 1.3 compliant

System Management
Little Endian format support
System operating clock generation
- Two on-chip PLLs, MPLL & UPLL
- MPLL generates the system reference clock, 200MHz@1.3V
- UPLL generates clocks for the USB Host/Device, IrDA and Camera
Power Management
- Clock-off control for individual components
- Various power-down modes are available such as IDLE, STOP and SLEEP
- Wake-up by one of external interrupts or by the RTC alarm interrupt, etc.

Electrical Characteristics
Operating Conditions
- Supply Voltage for Logic Core: 1.3V ± 0.05V
- External Memory Interface: 1.9V / 2.5V / 3.3V
- External I/O Interface: 3.3V
Operational Frequency
- Max. 200MHz@1.3V

Package
337-pin FBGA (0.5mm pitch, 13mm x 13mm)
 
 

 
Third Party Information
MERITECH Co, Ltd. (World Wide)
Official S3C24A0 Development Board (SMDK24A0)
VP of Business Evaluation Board Third Party
514, 5th Fl, #23 Yangjae-dong, Seocho-gu, Seoul 137-130 Korea
Home page : http://www.mcukorea.com
http://www.meritech.co.kr
E-mail : sales@meritech.co.kr
Tel: +82-2-576-8203 (104, 105)
Fax: +82-2-2057-7868
 
Production Status
 
: [ Under Development(Q3, '04) ]
General Download file
 
DOCUMENTS
File
Rev #
Size
Updated Date
0.5
6.05 MB
2005-03-14
 
2.06 MB
2004-01-26
TOOLS
EVALUATION  BOARD
 
File
Rev #
Size
Updated Date
0.0
8.33 MB
2004-05-17
0.1
2.68 MB
2004-05-17
0.62
446.03 KB
2004-05-17